The die area demands for registers depends upon their complexity. If the register is relatively simple, it may be constructed with fewer transistors and thus demands less die space. On the other hand, a user may require greater functionality from a register such as a clock enable (CE), a synchronous set/reset, and an asynchronous set/reset capability. It is conventional to provide such a rich set of functionality to a register using a relatively large number of transistors. But the resulting design then suffers from loss of density. In addition, a conventional register implements a clock enable function by recycling its registered output signal as an input signal that is then registered responsive to the clock. The register is thus cycling according to the clock even when the clock enable signal is de-asserted, which wastes power.
Accordingly, there is a need in the art for more robust register architectures that provides a full set of controls with increased density and low power consumption.
Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.